By Bruno Zatt, Muhammad Shafique, Sergio Bampi, Jörg Henkel (auth.)
This booklet indicates readers tips on how to increase energy-efficient algorithms and architectures to let high-definition 3D video coding on resource-constrained embedded units. clients of the Multiview Video Coding (MVC) usual face the problem of exploiting its 3D video-specific coding instruments for expanding compression potency on the expense of accelerating computational complexity and, therefore, the power intake. This booklet permits readers to lessen the multiview video coding power intake via together contemplating the algorithmic and architectural degrees. insurance contains an creation to 3D movies and an in depth dialogue of the present cutting-edge of 3D video coding, in addition to energy-efficient algorithms for 3D video coding and energy-efficient structure for 3D video coding.
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Additional resources for 3D Video Coding for Embedded Devices: Energy Efficient Algorithms and Architectures
The SoCs in current commercial mobile devices such as smartphones and tablets implement heterogeneous multicore SoCs employing processors with SIMD extensions, DSPs, ASIC codecs or hardware accelerators, and programmable embedded GPUs. Qualcomm Snapdragon S4 (Qualcomm Inc. 2011) is composed of up to 4 ARM cores, Hexagon DSPs, video coding hardware accelerators, and the Adreno embedded GPU. Nvidia Tegra 3 (Nvidia Corp. 2012) is based on up to 4 ARM cores and employs dedicated video encoder/decoder and ULP GeForce GPU.
On the one hand, ASIC solutions provide the highest performance and energy efficiency at the cost of reduced flexibility limiting the applicability to upcoming video standards. Still, the current lack of MVC-oriented ASIC optimizations prohibits further increase in both performance and energy efficiency. On the other hand, multimedia processors/DSPs allow high flexibility to multiple standards while providing reduced performance and poor energy efficiency if compared to ASICs. Additionally, reconfigurable processors may allow significant increase in performance and flexibility through instruction set architecture (ISA) extensions.
In this work the low power and sleep modes are data retentive avoiding data refetching, but it does not support partial DVS for specific sectors of the SRAM. Yamaoka et al. (2004) present a similar solution employing three operation modes while supporting bank-level DVS. It achieves leakage reduction through adapting the virtual supply voltage using PMOS transistors.
3D Video Coding for Embedded Devices: Energy Efficient Algorithms and Architectures by Bruno Zatt, Muhammad Shafique, Sergio Bampi, Jörg Henkel (auth.)